Smart pixel arrays for board-to-board optical interconnects can be utilised for backplane communications or 3-D packaging (distributed board-to-board communications). The former is considered the more immediate of the two, since it uses free-space optical beams to join SPAs on the extremities of printed circuit boards, rather than the present state-of-the-art, multi-level electrical interconnected boards.

3-D systems, on the other hand, are dispersed board-to-board optical interconnects that use the third dimension to enable global communication and may use holographic interconnect elements (very difficult with electrical interconnects).

High-speed smart pixel arrays (SPAs) have a lot of potential as a board-to-board interconnection technology in digital systems. SPAs are an expansion of an optoelectronic component class that has been around for over a decade, optoelectronic integrated circuits (OEICs).

The integration of electronic receivers with optical detectors and electronic drivers with optical sources or modulators has accounted for the great bulk of OEIC development.

Furthermore, only a single optical channel has been used in relatively little of this research. However, OEICs have been at the heart of much of the progress in serial fibre links. SPAs are an expansion of these optoelectronic components into arrays with signal processing capacity in each element of the array. As a result, an SPA can be defined as an array of optoelectronic circuits, each of which has the property of signal processing and, at the very least, optical input or output (most SPAs will have both optical input and output).

The term “smart pixel” is derived from standard electronics and refers to the presence of logic circuits. “Pixel” is an image processing term that refers to a small part, or quantized fragment, of an image. They define a wide range of gadgets when used together. These smart pixels can be nearly fully optical, perhaps manipulating optical data utilising the nonlinear optical features of a material, or they might be primarily electronic, such as a photoreceiver with some electronic switching.

Free space optical interconnects can boost throughput capacity while reducing energy consumption in ‘all electronic’ systems. Integrating optoelectronic devices with traditional electronics can result in high-speed optical interconnects. Optical interconnects have been developed for smart pixel arrays. A vertical cavity surface emitting laser (VCSEL), a photodetector, an optical receiver, a laser driver, and digital logic circuitry make up a single smart pixel cell. Oxide-confined VCSELs with a threshold current of about 1 mA are being developed to operate at 850 nm. AlGaAs quantum well photodetectors are being made in large quantities for usage with 850 nm VCSELs. Flip-chip bonding is used to integrate the VCSELs and photodetectors with complementary metal oxide semiconductor (CMOS) circuits.

A 32 X 16 smart pixel array is being combined with CMOS electronics. The 512 smart pixels are coupled in a serial manner. As a result, a whole data stream can be timed and electrically produced by the last pixel. The CMOS smart pixel array is undergoing electrical testing. A digital data sequence was cycled through the device validating operation of the digital circuitry using an on-chip pseudo random number generator. Despite the fact that the prototype device was made with 1.2 micrometre technology, calculations show that the array can run at 1 Gb/s per pixel with 0.5 micrometre technology.

Smart-Pixel Array Processors Based on Optimal Cellular Neural Networks for Space Sensor Applications

For advanced space sensor applications, a smart-pixel cellular neural network (CNN) with hardware annealing capabilities, digitally configurable synaptic weights, and multisensor parallel interface is being developed. The smart-pixel CNN architecture is a multi-dimensional array of programmable optoelectronic neurons that are coupled locally to their local neurons and active-pixel sensors. Integration of a neuroprocessor in each processor node of a scalable multiprocessor system improves on-board real-time intelligent multisensor processing and control tasks of advanced small satellites by orders of magnitude. The theory, architecture, design, and implementation of smart-pixel CNN operations, as well as system applications, are all examined in depth.

A prototype smart-pixel 5×5 neuroprocessor array device with active dimensions of 1380 micron x 746 micron in 2-micron CMOS technology demonstrated the VLSI (Very Large Scale Integration) implementation viability.


A laser micro-milling approach is used to produce a pixel array device under rigorous process control conditions. An array of pixels is bound together with an adhesive that fills the grooves between neighbouring pixels on the device. The array is made by moving a substrate at a controlled, constant velocity along a predetermined path defining a set of grooves between adjacent pixels so that a predetermined laser flux per unit area is applied to the material, and then repeating the movement for a number of passes of the laser beam until the grooves are ablated to the desired depth. In one case, the substrate is made of ultrasonic transducer material and is used to make a 2D ultrasonic phase array transducer. An X-ray focal plane array detector is made from a phosphor material substrate.


Several SPA technologies are fast advancing to the point where they can be used in full-scale optoelectronic systems. These SPA technologies can be divided into two categories: modulator-based smart pixels and source-based smart pixels. The modulator-based SPAs were the first to be created, and various demonstration systems have used them. As the features of VCSELs improve, source-based SPAs are rapidly emerging. In the section below, we’ll go over both of these types of SPAs.

Smart Pixels with a Modulator

The first SPA technologies were built around the monolithic integration of photodetectors, electronics, and modulators into a single device.

The modulator-based SPAS has two significant advantages:

1) They are simple devices that must be dependable, reproducible, and consistent.

2) The input light (power supply) can be regulated from a central location, making system synchronization easier.

The required connecting optics are substantially more complicated, which is a huge disadvantage.

The FET-SEED Hybrid CMOS-SEED and liquid-crystal-on-silicon technologies are the three key SPA technologies addressed in this section.

1) ET-SEED Smart Pixels: ET-SEED was the first smart pixel technology to monolithically incorporate the following features:

1) GaAs-AL, Gal-,As-based multiple-quantum-well (MQW) reflection modulators, integrated resistors as an option

2) photodetectors that use the same MQW stack as the modulators.

3) MIS-like field effect transistors with doped channels (DMT).

4) integrated resistors as an option

The DMT channel, the quantum well absorption region for both the modulators and photodetectors, the doped n- and p-type contact layers, and the dielectric mirrors required by the reflection modulators are all grown using a single molecular-beam epitaxial (MBE) development sequence. Reflection modulators were employed to create a framework that was suited for batch production while also allowing for heat sinlung on the chip’s reverse side. In order to maintain a steady excitonic absorption wavelength, heat sinking is required. To construct larger and more intricate functional circuits, these basic circuit pieces were stitched together using buffered FET logic (BFL).

Smart Pixels with Hybrid CMOS-SEED:

Individual optical logic gates will not be able to compete with existing or future silicon electronics technology platforms in terms of power consumption, device size, or system complexity, according to the Hybrid CMOS-SEED technologies. It has also become clear that silicon electronics will continue to improve in terms of performance and complexity while decreasing in cost. Instead of competing with this fast evolving technology, smart pixel technology aims to complement it. Because connectivity is the added value of optics in the digital electronic arena, offering optical inputs and outputs for existing electronic integrated circuit platforms became the driving force behind the technologies.

The first attempt at integrating modulators/photodetectors onto silicon circuits was to use silicon CMOS devices with InGaAs modulators [15]. AT&T [16] pursued the use of GaAs-A1,Gal -,As modulators/photodetectors on silicon CMOS. MQW modulators/photodetectors are built on GaAs chips in this technique, with the n and p contacts coplanar (see Fig. 6). To operate as a 40 percent reflector, a Ti-Au pad is deposited at the location of the optical windows of the MQW modulators/photodetectors. The electrical contacts of the modulators/photodetectors are then deposited with a lead-tin alloy for flip-chip bonding between the two substrates. The MOSIS foundry provided the silicon CMOS chips for the project (both 1.2-pm and 0.8-pm line rules have been used).

The CMOS chip’s aluminium bonding pads are next coated with a thin Ti-Pt-Au layer to produce a solder-wetable surface for eventual solder bump bonding. The two chips are then soldered together using a flip-chip method. A silica-filled epoxy is wicked between the chips before the GaAs substrate is removed to protect both the GaAs and silicon chips. The GaAs substrate is then etched away, leaving just the tiny MQW modulators/photodetectors on the chip in the desired positions. After that, an antireflection coating is put to the entire chip. A CMOS-SEED SPA in close-up. It should be noted that this technology is not restricted to silicon CMOS; it may also be applied to other silicon circuit families such as ECL, bipolar, BiCMOS, and so on.

MSM/MESFETNCSEL Monolithic Smart Pixels: The monolithic integration of VCSELs, MSM detectors, and MESFET transistors is the foundation of the GaAs MSMIMESFETNCSEL smart pixel. The output device in each smart pixel in this NTT-invented smart pixel technology is optical sources rather than modulators. Smart pixels based on this technique have achieved 220 MHz bandwidths with a 3-dB bandwidth. A simple monolithically integrated MSMMESFETNCSEL smart pixel is shown in Figure 12.

Flip-Chip Bonded VCSEUMSM Smart Pixels: Instead of modulators, flip-chip bonding VCSELs to an electronic substrate is a natural evolution of the Hybrid-SEED technology.


  • In the fields of image processing, data processing, and digital signal processing, SPAs have a plethora of applications.
  • Smart-pixel arrays, which integrate very specific functionality at the pixel level, are used in many applications that require high throughput picture capture.
  • In industrial automation applications, 3D image sensors with smart pixel arrays are utilised to analyse size, shape, and volume.
  • Optical datainterconnect and optical memory access are also possible with smart pixel arrays.


  • Smart pixel arrays use high-speed switching to achieve high data transfer rates.
  • Cross-talk is reduced with smart pixel arrays because interference is almost eliminated.
  • When compared to today’s copperwires, smart pixel interconnects are lighter since they are comprised of feather-light fibre ribbons.
  • Smart pixel arrays allow for faster processing while using substantially less optical power.


  • The most significant problem that smart-pixel technology faces is financial.
  • There are some potential issues with getting the electrical design to interface with the optics.
  • Because photodetectors have a poor efficiency, they have a slower switching speed, which reduces the data transfer rate.
  • Due to manufacturing flaws, non-uniformity may occur.


Thus, the ability to perform parallel processingof large pixelated images and in real-time reduce a complex image into a manageable stream of signals that can be brought off-chip has driven smart pixel arrays, the integration of photodetectorarrays and processing electronics on a single semiconductor chip. Smart pixel arrays will also enhance data retrieval rates by orders of magnitude.

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