Crusoe Processor

The microprocessor is at the heart of any computer, whether it’s a desktop or a mobile device. Microprocessors for desktop PCs are available from firms such as Intel, AMD, Cyrix, and others. There has never been a CPU specifically developed for mobile computing.

The microprocessors found in mobile computers are optimised versions of those found in desktop computers. The demands placed on processors by mobile computing are substantially different from those placed on processors by desktop computing.

Those desktop PC processors use a lot of energy and get quite hot. When you’re on the go, a power-hungry processor implies one of two things: you’ll run out of power before you’ve done, or you’ll have to lug pounds of extra batteries through the airport.

A hot processor necessitates the use of fans to keep it cool, resulting in a larger, clunkier, and noisier mobile computer. If the performance of a newly built microprocessor with low power consumption is unsatisfactory, the market will reject it. To be commercially successful, every approach in this area must have an appropriate ‘performance-power’ balance.

Because the majority of currently available software is designed to run on the x86 platform, a newly developed microprocessor must be fully x86 compatible, that is, it must run x86 applications just like ordinary x86 microprocessors.

Crusoe is a novel microprocessor that was created with the mobile computer market in mind. It has been created with the above-mentioned constraints in mind. This microprocessor was created by Transmeta Corp, a modest Silicon Valley firm. Crusoe’s concept is easily grasped because to a simple diagram of the processing architecture, dubbed ‘amoeba.’

The x86 architecture is viewed as an ill-defined amoeba with features such as segmentation, ASCII arithmetic, variable-length instructions, and so on. Crusoe was designed as a hybrid microprocessor, meaning it contains both a software and a hardware component, with the software layer encircling the hardware unit.

Software’s job is to operate as an emulator, converting x86 binaries to native code at runtime. Crusoe is a CMOS microprocessor with a 128-bit address space. To maintain design simplicity and great performance, the device uses a technology known as VLIW.

Code Morphing Software and LongRun Power Management are the other two technologies in use. Without harming legacy x86 software, the Crusoe hardware can be drastically changed: The hardware designers chose minimal space and power for the first Transmeta products, the models TM3120 and TM5400.

The Hybrid Approach to Crusoe Processors

The Crusoe processor is made up of a hardware engine that is logically surrounded by Code Morphing software. The CPU is a VLIW (very long instruction word) CPU, which means it can perform up to four operations per clock cycle.

The native instruction set is unrelated to the x86 instruction set and was created solely for low-power implementation. The software layer that surrounds x86 applications creates the idea that it is running on x86 hardware.

Some functions have been implemented in hardware, while others have been implemented in software, and this concept has changed the way microprocessors are designed.

Upgrades to a microprocessor’s software can be transmitted independently of the chip itself. Hardware designers can adapt and eventually replace their designs without disrupting legacy software by decoupling hardware design from the system and application software that uses it.

Improved versions of the Code Morphing software can even be downloaded into processors in the field, because it is normally stored in ordinary Flash ROMs on the motherboard. (The Code Morphing software copies itself from ROM to DRAM during initialization for optimum speed.)

CPU with VLIW (Very Log Instruction Word) instruction set:

Two integer units, a floating-point unit, a memory (load/store) unit, and a branch unit are all included in the CPU VLIW Engine. A molecule, or long instruction word, in the Crusoe processor can be 64 bits or 128 bits long and include up to four RISC-like instructions, or atoms.

The molecular format directly specifies how atoms are routed to functional units, which considerably simplifies the decode and dispatch hardware. There is no complex out-of-order hardware because molecules are executed in order.

Molecules are packed as densely as possible with atoms to keep the processor functioning at full speed. The integer register file contains 64 registers, numbered r0 through r63, some of which are assigned to keep x86 state, while others include system state or can be utilised as temporary registers.

Crusoe processors also include on-chip L1 and L2 caches of up to 128 KB and 256 KB, respectively. Crusoe does not require active cooling and can play a DVD at temperatures as low as 48°C! (Compare this to the Pentium III Processor’s outrageously high 105.5 C for the same performance, and you’ll see the difference!)

The Software for Code Morphing:

The Code Morphing software is a dynamic translation system, which translates instructions for the x86 target instruction set architecture (x86 ISA) into instructions for the VLIW host instruction set architecture (VLIW host ISA) at runtime.

The Code Morphing programme is stored in ROM and is the first programme to run when the CPU starts up. It optimises a translation by translating a full group of x86 instructions at once (a superscalar x86 translates single instructions in isolation).

Furthermore, although a standard x86 translates each instruction each time it is executed, instructions on a Crusoe are only translated once, and the resulting translation is retained in a translation cache, utilising the code’s Locality of Reference attribute.

The system skips the translation process the next time the (already translated) x86 code is executed, instead executing the existing optimised translation straight. Not all pieces of code are translated in the same way: x86 code can be executed in a variety of ways, from interpretation (which has no translation overhead but executes x86 code more slowly), through translation using relatively simple-minded code creation, to highly efficient code (which takes longest to generate, but which runs fastest once translated).

This procedure is improved by dynamic feedback information acquired during the execution of the code. Because Crusoe technology was specifically designed with dynamic translation in mind, it can achieve great performance in dynamic translation when compared to other x86 processors.

“The software-translation approach’s versatility comes at a cost: the processor must spend some of its cycles to running the Code Morphing programme, cycles that would otherwise be employed”
However, the benefits of such a strategy significantly exceed the drawbacks.

Power Management in the Long Run:

LongRun Power Management is a feature of the Crusoe TM5400 processor that helps to reduce the processor’s already low power usage. Most traditional x86 CPUs control their power consumption in a mobile environment by rapidly alternating between running at full speed and turning the processor off. The processor, on the other hand, may be turned off just as a time-critical programme requires it.

The TM5400, on the other hand, can modify its power usage without turning itself off; instead, it modifies its clock frequency on the fly, without requiring a reboot of the operating system.

As a result, software may continuously monitor the processor’s demands and dynamically select the ideal clock speed (and thus power consumption) for the programme to function.

Over the next few years, the importance of the hybrid approach to microprocessor design will certainly become clearer. Compared to traditional hardware-only designs, the technology allows for more innovation (both hardware and software). The strategy isn’t confined to low-power or x86-compatible processors.

Crusoe processors, which were originally aimed at the mobile computing sector, can enable devices like mobile computers and Internet access devices PC capabilities with unplugged running durations of up to a day.

Crusoe processor architecture

TM3120, TM3200, TM5400, and TM5600 are the Crusoe microprocessor variants available on the market. Except for a few small differences, all of the above models have the same core architecture, despite the fact that numerous models have been introduced for different areas of the mobile computing market.

Crusoe TM5400 was used as a model for the following architectural description. Integer and floating point execution units, independent instruction and data caches, a level-2 write-back cache, a memory management unit, and multimedia instructions are all included in the Crusoe Processor.

There are certain extra units, which are normally part of the core system logic that surrounds the microprocessor, in addition to these traditional processor characteristics.

The Crusoe CPU can provide a highly integrated, ultra-low power, high performance platform solution for the x86 mobile market thanks to the VLIW processor, Code Morphing software, and extra system core logic units.

Core of the Processor

By normal standards, the Crusoe Processor’s core architecture is quite simple. It is based on the VLIW instruction set, which is 128 bits long. The processor’s control logic is kept simple in this VLIW architecture, and software is employed to regulate the scheduling of instructions. With an in-order 7-stage integer pipeline and a 10-stage floating-point pipeline, a simplified and fairly basic h/w solution is possible.

The performance-to-power consumption ratio can be considerably improved over typical x86 architectures by simplifying the processor h/w and decreasing the control logic transistor count.

An 8-way set-associative Level 1 (L1) instruction cache and a 16-way set-associative L1 data cache are included in the Crusoe Processor. It also has a built-in Level 2 (L2) write-back cache for increased effective memory bandwidth and speed.

This cache architecture ensures maximal internal memory bandwidth for performance-intensive mobile applications while preserving the same low-power implementation that outperforms earlier x86 implementations in terms of performance-to-power consumption ratio.

Aside from having execution hardware for logical, arithmetic, shift, and floating point instructions, the Crusoe differs from traditional x86 architectures in a number of ways. The h/w generates the same condition codes as traditional x86 processors and operates on the same 80-bit floating-point numbers to make the transition from x86 to the core VLIW instruction set easier.

The TLB also has the same protection bits and address mapping as an x86 CPU. This solution’s software component is utilised to simulate all other aspects of the x86 architecture. The CMS is the software that translates x86 programmes into core VLIW instructions.

DDR SDRAM Memory Controller Integrated

The Crusoe’s DDR SDRAM interface is the fastest memory interface available. Only Double Data Rate (DDR) SDRAM is supported by the DDR SDRAM controller, which transfers data at double the interface’s clock frequency.The TM 3200 does not have this feature.

The DDR SDRAM controller supports up to four banks of DDR SDRAM utilising a 64-bit wide interface, which is the equivalent of two Dual In-line Memory Modules (DIMMs).

64M-bit, 128M-bit, and 256M-bit devices can be used to fill the DDR SDRAM memory. During the power-on startup procedure, the DDR SDRAM interface’s frequency setting is configured.

SDRAM Memory Controller with SDR Integrated

The SDR SDRAM memory controller can support up to four banks of Single Data Rate (SDR) SDRAM, which are comparable to two Small Outline Dual In-line Memory Modules (SO-DIMMS) and can be configured as 64-bit or 72-bit SO-DIMMs. 64M-bit, 128M-bit, and 256M-bit devices can be used in these SO-DIMMs.

There are no restrictions on mixing multiple SO-DIMM configurations into each SO-DIMM slot, but all SO-DIMMs must use the same frequency SDRAMs. During the power-on startup procedure, the frequency setting for the SDR SDRAM interface is initialised.

PCI Controller Integrated

A PCI bus controller that is PCI 2.1 compatible is included with the Crusoe Processor. The PCI bus is 32 bits wide, runs at 33 MHz, and can handle 3.3V signal levels. It is not, however, 5V tolerant. A PCI host bridge, a PCI bus arbiter, and a DMA controller are all provided by the PCI controller.

Interface to a Serial ROM

A five-pin interface called the Crusoe serial ROM interface is used to read data from a serial flash ROM. The CMS’s non-volatile storage is provided by the 1M-byte flash ROM. The Code Morphing code is copied from the ROM to the Code Morphing memory area in SDRAM during the boot process.

The Code Morphing code requires 8 to 16 Mbytes of memory space once it has been trans-erred. To x86 programmes, the section of SDRAM dedicated for CMS is invisible. For the flash ROM device, Transmeta provides programming information. This interface can also be used to reprogramme the flash ROM in the system.


Features of the Crusoe Processor Model TM3200

• The VLIW processor and x86 Code Morphing software work together to create an x86-compatible mobile platform.

• The processor’s core runs at 366 or 400 MHz.

• A 64K-byte instruction cache and a 32K-byte data cache are integrated.

• Compact system designs are made possible by integrated Northbridge core logic characteristics.

• 66-133 MHz SDR SDRAM memory controller with 3.3V interface

• PCI (Peripheral Component Interface) bus controller with 33 MHz and 3.3V interface (PCI 2.1 compatible)

• Longer battery life thanks to advanced power management technologies and ultra-low power operation

• Support for the full System Management Mode (SMM)

• Ceramic BGA (Ball Grid Array) packaging with 474 pins.

Model TM5400 Crusoe Processor

• The VLIW processor and x86 Code Morphing software give a mobile platform solution that is x86 compatible.

• The processor core operates at a frequency of 500-700 MHz.

• 64K-byte L1 instruction cache, 64K-byte L1 data cache, and 256K-byte L2 write-back cache are all integrated into the north bridge core logic, allowing for more compact system designs.

• 100-133 MHz DDR SDRAM memory controller with 2.5V interface

• 66-133 MHz SDR SDRAM memory controller with 3.3V interface

• 33 MHz, 3.3V interface PCI bus controller (PCI 2.1 compatible)

• Advanced power management with ultra-low power operation extends the life of mobile batteries with LongRun! Running normal multimedia programmes at 1-2 W @ 500-700 MHz, 1.2-1.6V! In profound sleep, 50 mW.

• Support for the full System Management Mode (SMM)

• Ceramic BGA package with 474 pins in a small package

Features of the Crusoe Processor Model TM5600

• The VLIW CPU and x86 Code Morphing software deliver an x86-compatible mobile platform. The processor core operates at a frequency of 500-700 MHz.

• A 64K-byte L1 instruction cache, a 64K-byte L1 data cache, and a 512K-byte L2 write-back cache are all built into the processor.

• Compact s/m designs are made possible by integrated north bridge core logic characteristics.

• DDR SDRAM memory controller with a 100-133 MHz interface and a 2.5V supply.

• 66-133 MHz SDR SDRAM memory controller with 3.3V interface

• 33 MHz, 3.3V interface PCI bus controller (PCI 2.1 compatible)

• Advanced power management with ultra-low power operation extends the life of mobile batteries with LongRun! Running normal multimedia programmes at 1-2 W @ 500-700 MHz, 1.2-1.6V! In profound sleep, 100 mW.

• Support for the full System Management Mode (SMM)

Compatibility of Software

The Crusoe CPU, when combined with Transmeta’s x86 Code Morphing software, allows for x86-compatible programme execution without the need for code recompilation. All standard x86-compatible operating systems and applications, including Microsoft Windows 9x, Windows ME, Windows 2000, and Linux, can be run on computers based on this technology.


In mobile computing, users have been forced to choose between battery life and performance due to complex power-hungry processors. Crusoe processors are developed for lightweight (two to four pound) mobile computers and Internet access devices like handhelds and web pads. They can give these devices PC capabilities and allow them to run for up to a day without being plugged in.

Crusoe processor chips were redesigned utilising microprocessor design principals. Choose a cutting-edge strategy that combines hardware and software in a novel way. Millions of logic transistors are saved and power consumption is reduced by using software to deconstruct complex instructions into simple atoms and schedule and optimise the atoms for parallel execution.

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